FPGA implementation of a postquantum key encapsulation mechanism using HLS
Post-Quantum Cryptography; PQC; CRYSTALS-Kyber; accelerator; FPGA; HLS.
This dissertation presents the specification of an accelerator for CRYSTALS-Kyber, the first Key Encapsulation Mechanism (KEM) standardized by the National Institute of Standards and Technology (NIST) as Post-Quantum Cryptography (PQC). The accelerator was developed with high-level synthesis (HLS) and it is composed of the encryption and decryption operations present in the KEM Kyber encapsulation and decapsulation algorithms. The developed architecture makes use of 33733 LUTs, 22810 FFs and 151 DSPs, being implemented in a low cost FPGA PYNQ-Z1 (XC7Z020-1 CLG400C). In a key exchange simulation performed with the Vitis HLS tool, the accelerator spent a total time of approximately 3.81 milliseconds, operating at 100MHz. In this simulation, the architecture developed had an estimated consumption of 2.243W of power. With the implementation of the accelerator in the FPGA, the observed time to perform the encryption and decryption operations was 5.01 and 2.24 milliseconds, respectively. The energy consumption in this process was approximately 6.2 Joules